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features at +2.7v ?0 a supply current per channel 1.2mhz gain bandwidth product output voltage range: 0.01v to 2.69v input voltage range: -0.25v to +1.5v 1.5v/ s slew rate LMV321 directly replaces other industry standard LMV321 amplifiers; available in sc70-5 and sot23-5 packages lmv358 directly replaces other industry standard lmv358 amplifiers; available in msop-8 and soic-8 packages lmv324 directly replaces other industry standard lmv324 amplifiers; available in tssop-14 and soic-14 packages fully specified at +2.7v and +5v supplies operating temperature range: -40? to +125? applications low cost general purpose applications cellular phones personal data assistants a/d buffer dsp interface smart card readers portable test instruments keyless entry infrared receivers for remote controls ? elephone systems audio applications digital still cameras hard disk drives mp3 players description the LMV321 (single), lmv358 (dual), and lmv324 (quad) are a low cost, voltage feedback amplifiers that consume only 80 a of supply current per amplifier. the lmv3xx family is designed to operate from 2.7v (1.35v) to 5.5v (2.75v) supplies. the common mode voltage range extends below the negative rail and the output provides rail-to-rail performance. the lmv3xx family is designed on a cmos process and provides 1.2mhz of bandwidth and 1.5v/ s of slew rate at a low supply voltage of 2.7v. the combination of low power, rail-to-rail performance, low voltage operation, and tiny pack- age options make the lmv3xx family well suited for use in personal electronics equipment such as cellular handsets, pagers, pdas, and other battery powered applications. LMV321, lmv358, lmv324 general purpose, low voltage, rail-to-rail output amplifiers www.fairchildsemi.com rev. 1 november 2002 + - lmv3xx r f 0.01 f 6.8 f out +in +v s + r g ty pical application frequency response vs. c l magnitude (1db/div) frequency (mhz) 0.01 0.1 1 10 c l = 200pf r s = 0 c l = 20pf r s = 0 c l = 200pf r s = 225 ? c l = 100pf r s = 0 c l = 10pf r s = 0 c l = 2pf r s = 0 c l = 50pf r s = 0 + - 10k ? 10k ? r s c l 2k ?
da ta sheet LMV321/lmv358/lmv324 2 rev. 1 november 2002 LMV321 ? + 1 2 3 +in -v s -in +v s out 5 4 ? + 1 2 3 +in -v s -in +v s out 5 4 sc70-5 lmv358 - + - + 1 2 3 4 out1 -in1 +in1 -v s +v s out2 -in2 +in2 8 7 6 5 msop-8 - + - + 1 2 3 4 out1 -in1 +in1 -v s +v s out2 -in2 +in2 8 7 6 5 soic-8 lmv324 1 2 3 4 out1 -in1 +in1 +v s out4 -in4 +in4 -v s 14 13 12 11 5 6 7 +in2 -in2 out2 +in3 -in3 out3 10 9 8 tssop-14 sot23-5 pin assignments 1 2 3 4 out1 -in1 +in1 +v s out4 -in4 +in4 -v s 14 13 12 11 5 6 7 +in2 -in2 out2 +in3 -in3 out3 10 9 8 soic-14
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 3 absolute maximum ratings p arameter min. max. unit supply voltages 0+6v maximum junction temperature ? +175 c storage temperature range -65 +150 c lead temperature, 10 seconds ? +260 c input voltage range - v s -0.5 +v s +0.5 v electrical specifications (t c = 25c, v s = +2.7v, g = 2, r l = 10k ? to v s /2, r f = 10k ? , v o (dc) = v cc /2; unless otherwise noted) p arameter conditions min. typ. max. unit ac p erformance gain bandwidth product c l = 50pf, r l =2k ? to v s /2 1.2 mhz phase margin 52 deg gain margin 17 db slew rate v o = 1v pp 1.5 v/ s input voltage noise >50khz 36 nv/ hz crosstalk: lmv358 100khz 91 db lmv324 100khz 80 db dc performance input offset voltage 1 1.7 7 mv av erage drift 8 v/c input bias current 2 <1 na input offset current 2 <1 na po w er supply rejection ratio 1 dc 50 65 db supply current (per channel) 1 80 120 a input characteristics input common mode voltage range 1 lo 0 -0.25 v hi 1.5 1.3 v common mode rejection ratio 1 50 70 db output characteristics output voltage swing r l = 10k ? to v s /2; lo 1 0.1 0.01 v r l = 10k ? to v s /2; hi 1 2.69 2.6 v min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. notes: 1. guaranteed by testing or statistical analysis at +25?. 2. +in and -in are gates to cmos transistors with typical input bias current of <1na. cmos leakage is too small to practically measure. recommended operating conditions p arameter min. max. unit operating temperature range -40 +125 c po w er supply operating range 2.5 5.5 v
da ta sheet LMV321/lmv358/lmv324 4 rev. 1 november 2002 electrical specifications (t c = 25c, v s = +5v, g = 2, r l = 10k ? to v s /2, r f = 10k ? , v o (dc) = v cc /2; unless otherwise noted) p arameter conditions min. typ. max. unit ac p erformance gain bandwidth product c l = 50pf, r l =2k ? to v s /2 1.4 mhz phase margin 73 deg gain margin 12 db slew rate 1.5 v/ s input voltage noise >50khz 33 nv/ hz crosstalk: lmv358 100khz 91 db lmv324 100khz 80 db dc performance input offset voltage 1 17mv av erage drift 6 v/c input bias current 2 <1 na input offset current 2 <1 na po w er supply rejection ratio 1 dc 50 65 db open loop gain 1 50 70 db supply current (per channel) 1 100 150 a input characteristics input common mode voltage range 1 lo 0 -0.4 v hi 3.8 3.6 v common mode rejection ratio 1 50 75 db output characteristics output voltage swing r l = 2k ? to v s /2; lo/hi 0.036 to 4.95 v r l = 10k ? to v s /2; lo 1 0.1 0.013 v r l = 10k ? to v s /2; hi 1 4.98 4.9 v short circuit output current 1 sourcing; v o = 0v 5 +34 ma sinking; v o = 5v 10 -23 ma min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. notes: 1. guaranteed by testing or statistical analysis at +25?. 2. +in and -in are gates to cmos transistors with typical input bias current of <1na. cmos leakage is too small to practically measure. pa ck ag e thermal resistance package ja 5 lead sc70 331.4c/w 5 lead sot23 256c/w 8 lead soic 152c/w 8 lead msop 206c/w 14 lead tssop 100c/w 14 lead soic 88c/w
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 5 non-inverting freq. response v s = +5v normalized magnitude (1db/div) frequency (mhz) 0.01 0.1 g = 10 1 10 g = 5 g = 1 g = 2 inverting frequency response v s = +5v normalized magnitude (1db/div) frequency (mhz) 0.01 0.1 g = -10 1 10 g = -5 g = -1 g = -2 non-inverting freq. response v s = +2.7v normalized magnitude (1db/div) frequency (mhz) 0.01 0.1 g = 10 1 10 g = 5 g = 1 g = 2 inverting freq. response v s = +2.7v normalized magnitude (1db/div) frequency (mhz) 0.01 0.1 g = -10 1 10 g = -5 g = -1 g = -2 frequency response vs. c l magnitude (1db/div) frequency (mhz) 0.01 0.1 1 10 c l = 200pf r s = 0 c l = 20pf r s = 0 c l = 200pf r s = 225 ? c l = 100pf r s = 0 c l = 10pf r s = 0 c l = 2pf r s = 0 c l = 50pf r s = 0 + - 10k ? 10k ? r s c l 2k ? frequency response vs. r l magnitude (1db/div) frequency (mhz) 0.01 0.1 1 10 r l = 1k ? r l = 2k ? r l = 100k ? r l = 10k ? small signal pulse response output (v) time ( s) 020 24681012141618 -0.05 0.1 0.25 0 0.05 0.2 0.15 large signal pulse response output (v) time ( s) 020 24681012141618 -0.5 0.1 2.5 0 0.5 2 1.5 t ypical operating characteristics (t c = 25c, v s = +5v, g = 2, r l = 10k ? to v s /2, r f = 10k ? , v o (dc) = v cc /2; unless otherwise noted)
da ta sheet LMV321/lmv358/lmv324 6 rev. 1 november 2002 input voltage noise nv/ hz frequency (khz) 1 10 100 1000 20 30 40 50 60 70 80 100 total harmonic distortion thd (%) frequency (khz) 0.1 1 10 100 0 0.1 0.2 0.3 0.4 0.5 0.6 v o = 1v pp open loop gain & phase vs. frequency open loop phase (deg) frequency (hz) 10m 10 100 100k 10k 1k 1m -270 -225 -180 0 -135 -45 -90 -20 0 20 100 40 80 60 open loop gain (db) |gain| phase r l = 2k ? c l = 50pf t ypical operating characteristics (t c = 25c, v s = +5v, g = 2, r l = 10k ? to v s /2, r f = 10k ? , v o (dc) = v cc /2; unless otherwise noted)
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 7 application information general description the lmv3xx family are single supply, general purpose, voltage-feedback amplifiers that are pin-for-pin compatible and drop in replacements with other industry standard LMV321, lmv358, and lmv324 amplifiers. the lmv3xx family is fabricated on a cmos process, features a rail-to-rail output, and is unity gain stable. the typical non-inverting circuit schematic is shown in figure 1. figure 1: typical non-inverting configuration po wer dissipation the maximum internal power dissipation allowed is directly related to the maximum junction temperature. if the maximum junction temperature exceeds 150?, some performance degradation will occur. if the maximum junction temperature exceeds 175? for an extended time, device failure may occur. driving capacitive loads the frequency response vs c l plot on page 4, illustrates the response of the lmv3xx family. a small series resistance (r s ) at the output of the amplifier, illustrated in figure 2, will improve stability and settling performance. r s values in the frequency response vs c l plot were chosen to achieve maximum band- width with less than 1db of peaking. for maximum flatness, use a larger r s . as the plot indicates, the lmv3xx family can easily drive a 200pf capacitive load without a series resistance. for comparison, the plot also shows the LMV321 driving a 200pf load with a 225 ? series resistance. driving a capacitive load introduces phase-lag into the output signal, which reduces phase margin in the amplifier. the unity gain follower is the most sensitive configuration. in a unity gain follower configuration, the lmv3xx family requires a 450 ? series resistor to drive a 200pf load. the response is illustrated in figure 3. figure 2: typical topology for driving a capacitive load figure 3: frequency response vs c l f or unity gain configuration layout considerations general layout and supply bypassing play major roles in high frequency performance. fairchild has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. follow the steps below as a basis for high frequency layout: include 6.8 f and 0.01 f ceramic capacitors place the 6.8 f capacitor within 0.75 inches of the power pin place the 0.01 f capacitor within 0.1 inches of the power pin remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance minimize all trace lengths to reduce series inductances refer to the evaluation board layouts shown in figure 5 on page 8 for more information. + - lmv3xx r f 0.01 f 6.8 f out +in +v s + r g + - 10k ? 10k ? r s c l 2k ? lmv3xx magnitude (db) frequency (m h z ) 0.01 0.1 1 10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 c l = 50pf r s = 0 c l = 100pf r s = 400 ? c l = 200pf r s = 450 ?
da ta sheet LMV321/lmv358/lmv324 8 rev. 1 november 2002 evaluation board information the following evaluation boards are available to aid in the testing and layout of this device: evaluation board schematics and layouts are shown in figures 4 and 5. eval bd description products keb013 single channel, dual supply, LMV321as5x sot23-5 for buffer-style pinout keb014 single channel, dual supply, LMV321ap5x sc70-5 for buffer-style pinout keb006 dual channel, dual supply, lmv358am8x 8 lead soic keb010 dual channel, dual supply, lmv358amu8x 8 lead msop keb012 quad channel, dual supply, lmv324amtc14x 14 lead tssop keb018 quad channel, dual supply, lmv324am14x 14 lead soic evaluation board schematic diagrams figure 4a: LMV321 keb013 schematic figure 4b: LMV321 keb014 schematic
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 9 evaluation board schematic diagrams (continued) figure 4c: lmv358 keb006/keb010 schematic figure 4d: lmv324 keb012/keb018 schematic
da ta sheet LMV321/lmv358/lmv324 10 rev. 1 november 2002 figure 5a: keb013 (top side) figure 5b: keb013 (bottom side) figure 5c: keb014 (top side) figure 5d: keb014 (bottom side) LMV321 evaluation board layout
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 11 figure 5g: keb010 (top side) figure 5h: keb010 (bottom side) lmv358 evaluation board layout figure 5e: keb006 (top side) figure 5f: keb006 (bottom side)
da ta sheet LMV321/lmv358/lmv324 12 rev. 1 november 2002 lmv324 evaluation board layout figure 5i: keb012 (top side) figure 5j: keb012 (bottom side) figure 5k: keb018 (top side) figure 5l: keb018 (bottom side)
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 13 LMV321 package dimensions b e e1 d c l e c l c l a a2 a1 e1 c 2 datum ?a? c l note: 1. all dimensions are in millimeters. 2 foot length measured reference to flat foot surface parallel to datum ?a? and lead surface. 3. package outline exclusive of mold flash & metal burr. 4. package outline inclusive of solder plating. 5. comply to eiaj sc74a. 6. package st 0003 rev a supercedes sot-d-2005 rev c. symbol min max a 0.90 1.45 a1 0.00 0.15 a2 0.90 1.30 b 0.25 0.50 c 0.09 0.20 d 2.80 3.10 e 2.60 3.00 e1 1.50 1.75 l 0.35 0.55 e 0.95 ref e1 1.90 ref 010 sot23-5 symbol min max e 0.65 bsc d1.80 2.20 b0.15 0.30 e1.15 1.35 he 1.80 2.40 q1 0.10 0.40 a2 0.80 1.00 a1 0.00 0.10 a 0.80 1.10 c 0.10 0.18 l 1.10 0.30 b e d c l he c l c l a a2 a1 e c c l note: 1. all dimensions are in millimeters. 2. dimensions are inclusive of plating. 3. dimensions are exclusive of mold flashing and metal burr. 4. all speccifications comply to eiaj sc70. l q1 sc70
da ta sheet LMV321/lmv358/lmv324 14 rev. 1 november 2002 lmv358 package dimensions h e c l zd c l e d pin no. 1 b a a1 a2 7 l detail-a detail-a c h x 45 note: 1. all dimensions are in millimeters. 2. lead coplanarity should be 0 to 0.10mm (.004") max. 3. package surface finishing: (2.1) top: matte (charmilles #18~30). (2.2) all sides: matte (charmilles #18~30). (2.3) bottom: smooth or matte (charmilles #18~30). 4. all dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side(d). symbol min max a1 0.10 0.25 b 0.36 0.46 c 0.19 0.25 d 4.80 4.98 e 3.81 3.99 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.41 1.27 a 1.52 1.72 0 zd 0.53 ref a2 1.37 1.57 8 soic-8 soic es e/2 2x e3 e4 12 ccc abc ? b ? 2 37 2 6 4 d2 a2 a a1 ? a ? ? c ? bbb ab c m b d 4 3 aaa a e1 ? h ? t1 t2 gauge plane 0.25mm r1 r l l1 03 02 01 detail a scale 40:1 section a - a b cc1 b1 e2 e1 e detail a 5 a a symbol min max a 1.10 a1 0.10 0.05 a2 0.86 0.08 d 3.00 0.10 d2 2.95 0.10 e 4.90 0.15 e1 3.00 0.10 e2 2.95 0.10 e3 0.51 0.13 e4 0.51 0.13 r 0.15 + 0.15/-0.06 r1 0.15 +0.15/-0.06 t1 0.31 0.08 t2 0.41 0.08 b 0.33 +0.07/-0.08 b1 0.30 0.05 c 0.18 0.05 c1 0.15 +0.03/-0.02 01 3.0 3.0 02 12.0 3.0 03 12.0 3.0 l 0.55 0.15 l1 0.95 bsc ? aaa 0.10 ? bb b 0.08 ? ccc 0.25 ? e 0.65 bsc ? s 0.525 bsc ? msop-8 ? note: 1a ll dimensions are in millimeters (angle in degrees), unless otherwise specified. 2 datums ? b ? and ? c ? to be determined at datum plane ? h ? . 3 dimensions "d" and "e1" are to be determined at datum ? h ? . 4 dimensions "d2" and "e2" are for top package and dimensions "d" and "e1" are for bottom package. 5 cross sections a ? a to be determined at 0.13 to 0.25mm from the leadtip. 6 dimension "d" and "d2" does not include mold flash, protrusion or gate burrs. 7 dimension "e1" and "e2" does not include interlead flash or protrusion. msop
LMV321/lmv358/lmv324 da ta sheet rev. 1 november 2002 15 e/2 2x ddd c b a 6 6 1.0 1.0 123 9 e /2 e1 e e n 8 ? b ? 7 2x n/2 tips 1.0 dia ? a ? 7 ? c ? aaa c ccc 8 3 d cb a bbb m b nx a1 a2 a c1 c (b) b1 5 section aa 10 a a ? h ? gage plane 0.25 (0.20) (02) r1 r 01 (l1) l (03) notes: 1 all dimensions are in millimeters (angle in degrees). 2 dimensioning and tolerancing per asme y14.5?1994. 3 dimensions "d" does not include mold flash, protusions or gate burrs. mold flash protusions or gate burrs shall not exceed 0. 15 per side . 4 dimension "e1" does not include interlead flash or protusion. interlead flash or protusion shall not exceed 0.25 per side. 5 dimension "b" does not include dambar protusion. allowable dambar protusion shall be 0.08mm total in excess of the "b" dimens ion at maximum material condition. dambar connot be located on the lower radius of the foot. minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. 6 te rminal numbers are shown for reference only. 7 datums ? a ? and ? b ? to be determined at datum plane ? h ? . 8 dimensions "d" and "e1" to be determined at datum plane ? h ? . 9 this dimensions applies only to variations with an even number of leads per side. for variation with an odd number of leads p er side, the "center" lead must be coincident with the package centerline, datum a. 10 cross sections a ? a to be determined at 0.10 to 0.25mm from the leadtip. symbol min nom max a ??1.10 a1 0.05 ? 0.15 a2 0.85 0.90 0.95 l 0.50 0.60 0.75 r 0.09 ? r1 0.09 ? b 0.19 ? 0.30 b1 0.19 0.22 0.25 c 0.09 ? 0.20 c1 0.09 ? 0.16 01 0? ?8 l1 1.0 ref aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 e 0.65 bsc 02 12?ref 03 12?ref tssop-14 d 4.90 5.00 5.10 e1 4.30 4.40 4.50 e 6.4 bsc e 0.65 bsc n 14 tssop lmv324 package dimensions h e c l zd c l e d pin no. 1 b a a1 a2 7 l detail-a detail-a c h x 45 note: 1. all dimensions are in inches. 2. lead coplanarity should be 0 to 0.10mm (.004") max. 3. package surface finishing: (2.1) top: matte (charmilles #18~30). (2.2) all sides: matte (charmilles #18~30). (2.3) bottom: smooth or matte (charmilles #18~30). 4. all dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side (d). symbol min max a1 .0040 .0098 b .014 .018 c .0075 .0098 d .337 .344 e .150 .157 e .050 bsc h .2284 .2440 h .0099 .0196 l .016 .050 a .060 .068 0 zd 0.20 ref a2 .054 .062 8 soic-14 soic
www.fairchildsemi.com ? 2002 fairchild semiconductor corporation ordering information model part number package container pack qty LMV321 LMV321ap5x sc70-5 reel 3000 LMV321 LMV321as5x sot23-5 reel 3000 lmv358 lmv358am8x soic-8 reel 2500 lmv358 lmv358amu8x msop-8 reel 3000 lmv324 lmv324amtc14x tssop reel 2500 lmv324 lmv324am14x soic reel 2500 t emperature range for all parts: -40c to +125c. da ta sheet LMV321/lmv358/lmv324 disclaimer f airchild semiconductor reserves the right to make changes without further notices to any products herein to improve reliabilit y, function or design. f airchild does not assume any liability arising out of the application or use of any product or circuit described herein; neithe r does it convey any license under its patent rights, nor the rights of others. life support policy f airchild?s products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of f airchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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